Computing devices are increasingly becoming more powerful and at the same time they are getting smaller; they are consuming less power and they possess exponentially more memory in relation to that which was done by their predecessor devices. For example, it is not uncommon today for a single user laptop to have more than one processor embedded in its chipset. In fact, recent industry pronouncements indicate that upwards of eighty processors have been successfully integrated into a single chipset design.
Having multiple integrated processors within a single chipset provides a variety of benefits. One obvious capability is parallel computing. That is, two or more threaded applications can execute at the same time and within the same device using different processors, thereby increasing processing throughput on that device.
Another benefit includes the establishment of multiple virtual machines from a single physical machine architecture. Although this is feasible with a single processor architecture, having a multiple processor architecture makes the creation and maintenance of virtual machines more practical. Additionally, the number of feasible virtual machines that can be executed on a single integrated device increases with a multiple processor architecture design.
Yet, one issue with a multiple processor architecture is that different virtual machines or threaded applications from different virtual machines can experience congestion or bottleneck situations within some processors or even between communication channels associated with the multiple processors. So, proactive maintenance, support, analysis, and load balancing are existing problems associated with the multiple processor architecture design.
Accordingly, there is a need for improved utilization planning and analysis that is associated with multiple processor architectures.